The present invention relates to a AND circuit for use in an emitter coupled logic system which avoids the use of transistor stacking.
Emitter coupled logic is a type of logic in which transistors are operated either in an active or in an OFF region and current is `steered` rather than having voltages or levels passed around. Speed is the primary purpose for using ECL logic. Typically, ECL circuitry operates off of a negative supply voltage of about -5.2 volts and might operate between input logic levels of -1.55 volts and -0.75 volts. In designing an AND function with such a circuit stacked logic is used. Since each section of a stack requires an additional -0.8 volts towards V.sub.EE, the maximum number of inputs for such an AND circuit is 3.
Schottky current mode logic (SCML) which operates with a -2.0 volt supply places even more severe constraints on a stacked AND gate system. In the latter case stacked gates cannot be used since there is not enough voltage available.
Accordingly, it is an object of the present invention to provide a circuit operating on a low supply voltage which can incorporate a plurality of AND type inputs.